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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1998 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs7615 ccd imager analog processor features l 10-bit a/d converter l multi-sync ccd timing generator, handles imagers up to 1000 pixels wide l integrated correlated double sampler l 38 db automatic analog gain control l up to 90 db total gain adjust range l closed-loop fuzzy agc/exposure l code 16 black level clamp l i 2 c control bus l 4-phase vertical ccd timing signals l no ccd buffer amplifier required l master clock or crystal controlled description the cs7615 is a low-power analog front-end processor for standard four-color interline transfer ccd imagers. the architecture includes a correlated double sampler, agc amplifier, black-level clamp, 10-bit a/d converter, and a complete multi-sync ccd timing generator. the analog ccd imager output can be directly connected to the cs7615 input, which does not require an external buffer amplifier. the pixel data is double sampled for im- proved noise performance, and gain adjusted prior to being digitized by the a/d converter. feedback from the a/d converter holds the image black level at code-16 (assumes 8-bit data path), addressing itu-601 compli- ance issues. the multi-sync ccd timing generator is programmed via the i 2 c bus, and can be used with a wide range of interline transfer ccd imagers up to 1000 pixels wide. the cs7615 supports full itu-601 compli- ance for images up to 720 pixels wide, and is compatible with both ntsc and pal timing. the cs7615 is de- signed to be used along with either the cs7665 or cs7666 digital color-space processor for ccd camer- as, which generates a 4:2:2 component digital video output. ordering information CS7615-KQ 0 to +70 c 44-pin tqfp (10 mm 10 mm 1.6 mm) ccd output master clock cds/agc data out pll output register i 2 c block formatter a/d converter black level timing generator agc controller ccd timing signals i 2 c bus clocks out jul 98 ds231pp6
cs7615 2 ds231pp6 table of contents analog characteristics: ........................................................................... 3 digital characteristics: ............................................................................ 3 power consumption: .................................................................................... 3 control port characteristics: .............................................................. 4 switching characteristics: ...................................................................... 5 recommended operating characteristics: ....................................... 5 absolute maximum ratings:....................................................................... 5 general description .................................................................................. 6 overview ..................................................................................................... 6 interfacing the cs7615 with cs7665 or cs7666 ....................................... 6 operation .................................................................................................... 6 ccd timing generator ............................................................................... 8 vertical timing specifications ..................................................................... 8 horizontal timing specifications ................................................................. 8 description of operation ............................................................................. 9 automatic gain control ............................................................................... 9 correlated double sampling (cds) .......................................................... 11 analog to digital converter ....................................................................... 15 black level adjust to code 16 (10-bit code 64) ....................................... 15 formatter .................................................................................................. 15 serial control bus ................................................................................... 16 station address ........................................................................................ 16 write operations ................................................................................ 16 address set operation ....................................................................... 16 read operations ................................................................................ 16 register descriptions ............................................................................. 17 pin descriptions ......................................................................................... 30 package dimensions .................................................................................. 34
cs7615 ds231pp6 3 analog characteristics: (t a =25 c; v aa =v dd =5v; output load=30pf ) digital characteristics: (t a =25 c; v aa =v dd =5v; output load=30pf ) power consumption: (t a =25 c; v aa =v dd =5v; output load=30pf ) parameter symbol min typ max units dynamic performance integral non-linearity inl - 1 - lsb differential non-linearity dnl - 0.75 - lsb analog input analog input capacitance c in -10-pf automatic gain control maximum gain g max -20-db minimum gain g min -0-db gain increment d g - 78.4 117.6 mdb parameter symbol min typ max units logic inputs high-level input voltage v ih v dd -0.8 - - v low-level input voltage v il --0.8v input leakage current i in --10ma logic outputs high-level output source current @ v oh = v dd -0.4v i oh --1ma low-level output sink current @ v ol = 0.4v i ol --1ma 3-state leakage current i oz --10 m a parameter symbol min typ max units power dissipation p d -650-mw analog power supply current normal mode low-power mode i an i alp - - 99 63 - - ma ma digital power supply current normal mode low-power mode i dn i dlp - - 55 22 - - ma ma
cs7615 4 ds231pp6 control port characteristics: (t a =25 c; v aa =v dd =5v; output load=30pf ) parameter symbol min typ max units scl clock frequency f scl - - 100 khz bus free time between transmissions t buf 4.7 - - m s start condition hold time t hdst 4.0 - - m s clock pulse width high low t high t low 4.0 4.7 -- m s m s setup time for repeat start condition t sust 4.7 - - m s sdain hold time from scl falling t hdd 0-- m s sdain setup time from scl rising t sud 0.25 - - m s sdain and scl rise time t r --1.0 m s sdain and scl fall time t f --0.3 m s setup time for stop condition t susp 4.0 - - m s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda s cl figure 1. i 2 c timing diagram
cs7615 ds231pp6 5 switching characteristics: (t a =25 c; v ss =v dd =5v; output load=30pf ) recommended operating characteristics: absolute maximum ratings: specifications are subject to change without notice. parameter symbol min typ max units crystal frequency range f cry 6.75 27 mhz crystal oscillator duty cycle 40 60 % clko frequency f pix 6.75 13.5 mhz clk2xo frequency f dat 13.5 27 mhz clko duty cycle 50 % clk2xo duty cycle 50 % clk2xo falling edge to clko fa lling edge 4 8 ns fr clock (ccd reset gate clock) duty cycle 25 % h1 clock duty cycle 50 % h2 clock duty cycle 50 % parameter symbol min typ max units power supply voltage v aa , v dd 4.5 5.0 5.5 v gnda to gndd voltage differential 10 mv crystal frequency range 6.75 27 mhz analog input ac range (figure 2) v ac 01.65v analog input dc offset (figure 2) v dc 12 v analog input voltage (figure 2) a in 018v parameter symbol min max units power supply voltage v aa , v dd -0.3 7.0 v digital input voltage gndd-0.3 (v dd )+0.3 v analog input voltage - ain only a in gnda-(0.3) 20 v input current (except supply pins) 10 ma ambient temperature range -0 +70 c lead solder temperature (10sec duration) +260 c storage temperature range -65 +150 c gnd v ain v dc v ac feedthrough level figure 2. analog input
cs7615 6 ds231pp6 general description overview the cs7615 performs the analog functions in a four chip digital ccd camera. the four main chips include the ccd imager, the cs7615 ccd digitiz- er, the cs7665 or cs7666 color space processor, and a vertical drive interface-chip for the ccd im- ager. several ccd imagers (and their associated vertical drivers) can be used with the cs7615 digi- tizer and the cs7665 or cs7666 processor to form a simple and cost-effective ycrcb output format digital camera. the block diagram in figure 3 illus- trates the system interconnect. interfacing the cs7615 with cs7665 or cs7666 the cs7666 is a direct replacement for the cs7665. no board or software changes are needed for existing designs. however, slight changes to existing hardware and software are necessary to take advantage of the cs7666. see figure 4 and 5 and the cs7666 data sheet for more details. operation the cs7615 digitizer is designed to provide all necessary analog functions and conversion to digi- tal data of a standard ccd imager output signal as well as provide all the timing and control signals for the ccd imager. the architecture includes a correlated double sampler, variable gain amplifier with an integrated agc loop, black level clamp, 10-bit a/d converter, output formatter, and a com- plete multi-sync ccd timing generator. the output of the a/d converter ranges from code 004h to code 3fbh and the formatter adds special end-of- active-video (eav) and start-of-active-video (sav) codes to each line, making the output of the cs7615 similar to the description in the itu-656 recommendation. ccd cds/adc image processor timing i c 2 i c 2 2 7 9 +5 v +8 v to +12 v dc-dc converter cs7615 cs7665 or cs7666 4:2:2, h.656 video i c bus 2 vertical drive 512x480 cs4952 or cs4954 figure 3. typical 4-chip digital ccd camera xtal 32 33 cs7615 39 4 56 55 cs7665 clk2x0 clock clk0 10-bit data figure 4. cs7615/cs7665 interface xtal 33 32 xtalin cs7615 39 4 56 52 cs7666 nc clk0 10-bit data 55 clkin nc cclokg figure 5. cs7615/cs7666 interface
cs7615 ds231pp6 7 the eav/sav code definitions are consistent with an 8-bit data path. as per the itu-656 recommen- dation, the lsbs of the cs7615 are fractional bits which are not used when delivering 8-bit output da- ta. in 10-bit mode, all ten digital outputs can be connected directly to the cs7665. the output data format from the cs7615 formatter is shown in figure 6. the cs7615 also outputs two clocks, one at the pixel rate and the other at 2 the output pixel data rate (see pin description for clk2xo). the output of the formatter is avail- able at the pins d o[0..9] and it transitions at the fall- ing edge of the pixel rate clock clko. figure 7 shows the basic output timing diagram. the falling edges of clko lag the falling edges of clk2xo by 4 to 8 ns and both clocks have approximately 50% duty cycles. href 4t n b t 4t av*t blanking period active video eav code (10 bits) smpl. word 0 3ffh 1 000h 2 000h 3 binary 1 fv 1 p 3 p 2 p 1 p 0 00 blank code (10 bits) smpl. word 4 040h repeat above word sav code (10 bits) smpl. word 0 3ffh 1 000h 2 000h 3 binary 1 fv 0 p 3 p 2 p 1 p 0 00 during active video, f = field bit; 0 (odd field), 1 (even field) v = vertical blanking bit; 0 (active video lines), 1(vertical blanking) p 3 p 2 p 1 p 0 = error protection bits (as per itu-656). t = output pixel period samples of mosaic data; during vertical blanking, 040h. at reset or power down, 040h. figure 6. cs7615 output data format
cs7615 8 ds231pp6 ccd timing generator the ccd timing and control signal outputs are dic- tated by the programmable register settings. this allows for compatibility with a variety of ccds. the hsync signal is also output for use in a gen- lock configuration. the open-drain hclk can be used to clock dc-dc voltage converters which are typically used to generate the ccd imager bias voltages. the following description explains the various output signals provided to the vertical driv- er and ccd as well as the programmable parame- ters that may be set to control these signals. href* - horizontal reference signal. it stays high during the active video portion of the line. henb* - horizontal shift register clock enable signal. enables h1 and h2 out of analog tim- ing. clamp* - black clamp signal provided to the adc. v1x, v2x, v3x, v4x - vertical register shift clock. used both during vertical transfer and charge read out. vh1x, vh3x - ccd charge read out pulse. hclk - signal used by the dc - dc converter. in the normal mode, it is the same as href; in fast mode, it operates at about 16 of the hori- zontal line frequency and is reset at the begin- ning of href. hsync - horizontal sync signal. ofdx - overflow drain control clock. this signal sets the electronic shutter speed. vrst - vertical field reset signal. vref* - vertical reference signal. it is high during the active video lines. *internal signal on the cs7615 - not a chip output. vertical timing specifications the ccd array is read out alternately as odd and even fields with interlaced horizontal lines. thus each field has half the total number of horizontal rows. table 1 specifies the programmable vertical timings which are defined in figure 8. the timings vary based on odd or even field, 525 or 625 line ccd, and the manufacturer. horizontal timing specifications each horizontal row of the ccd is divided into several regions corresponding to the type of pixels present. different ccds have different numbers of pixels in each region and the timing signals must take this into account. the different pixel types in- clude optical black pixels (front and rear), dummy pixels, active video pixels, and blank video. the horizontal timing for the ccd is based on main- taining a fixed 63.5 m s horizontal line time. clk2xo clko d o[0..9] figure 7. cs7615 output data and clocks
cs7615 ds231pp6 9 table 2 specifies all of the programmable timing parameters related to horizontal timing signals. these parameters are defined in figure 9. figure 9 shows the timings for href, hsync, clamp, and henb. their relationship to differ- ent kinds of pixels on each horizontal row output from the ccd is also shown. the waveforms for these signals are repeated on every line. the hori- zontal shift register clocks, h1 and h2, operate at the clko frequency and are active throughout the horizontal line period except when henb is high. figure 10 shows the timings for the v1x through v4x signals. the specified waveforms repeat on every horizontal line except during the charge transfer line. during this line the ccd charge is read out and the timing is different as shown in fig- ure 11. in addition signals vh1x and vh3x are also required during charge read out as shown in figure 12. the overflow drain control signal is shown in fig- ure 13. the ofdx signal is used to control the electronic shutter timing of the ccd. shutter tim- ing for various settings of the shutter control is de- scribed in the register section of this document. description of operation the internal operation of the cs7615 can be sepa- rated into several distinct blocks. the following section provides an overview of how these blocks operate and interact. automatic gain control the pixel data entering the cs7615 from the ccd is scaled as determined by the automatic gain con- trol loop. by properly applying gain to the signal, the full range of the a/d converter is used. the in- vref* href fld vlo vle vbo: end of vref xso: charge transfer line xse: charge transfer line vbe: end of vref 1 not to scale figure 8. vertical timing signals -internal to cs7615 symbol description register vlo # of lines in odd field 33h, 39h vle # of lines in even field 34h, 39h vbo end of vref line # 36h, 39h xso charge transfer line # 38h, 39h vbe end of vref line # 35h, 39h xse charge transfer line # 37h, 39h table 1. ccd vertical timing specifications
cs7615 10 ds231pp6 ternal analog gain range is 38 db in steps of 0.078 db ideal. adjustments made in these small steps should cause no noticeable brightness change in the image from frame to frame. in addition to the internal analog gain, the control loop will vary the shutter speed through the ofdx output from 0 to - 54 db as it deems necessary. the agc algorithm uses a luma or mosaic histo- gramming technique in which the brightness of each pixel is binned into one of seven bins. the number of pixels in a bin will produce an error sig- nal that is then used to update the gain. the follow- ing parameters control the loop dynamics and are programmable to meet the needs of the user. pal bit: selects a pal or ntsc camera sys- tem. agc window: adjusts what portion of the frame is used for the agc algorithm. luma/mosaic: selects whether luma or mosaic data are used in the histogramming. href hsync clamp henb ccd output 0 hbpd active video hsnyr hsynf bc hstart hend optical black pixels inactive video active video hlen figure 9. timing diagram for href, hsync, clamp, and henb
cs7615 ds231pp6 11 flickerless mode: restricts the shutter speed to only flickerless values for the given system and environment. if the scene is too bright, the agc loop will select exposure settings shorter than the flickerless modes. pal environment: selects pal or ntsc envi- ronment. target value: adjusts the brightness threshold. a lower target results in the loop settling to a lower gain. max gain: sets a maximum gain value that will not be exceeded even if the target brightness has not been met. slew: controls the rate of decay of the gain as the agc loop slews because of light intensity variation. speed: controls the overall loop gain and thus speed of gain correction. min gain: sets the minimum on-chip gain al- lowed. this value should be used if the satura- tion voltage is less than 1.6v. correlated double sampling (cds) correlated double sampling, as applied to ccd- based imaging systems, is a method used to remove low-frequency noise from the output of a ccd im- ager leaving only the signal of interest. the cds is applied prior to amplification by the vga. href v1x v2x v3x v4x v1r v1f v2r v2f v3f v3r v4f v4r figure 10. vertical shift register signal timings
cs7615 12 ds231pp6 href v1x v2x v3x v4x href v1x v2x v3x v4x v2er v2ef v3ef v3er v4ef v4er (no pulse on v1x) odd field even field line #17 line #18 line #279 line #280 note: line #s shown here are for 525 line systems v3of v3or v2or v2of figure 11. vertical shift register signal timings for charge read out phase
cs7615 ds231pp6 13 href vh1x vh3x vh1f vh1r line #17 and #279 note: line #s shown are for 525 line system. vh3f vh3r figure 12. charge read out signal timing vref ofdx 19 h 262 h or 263 h horizontal line count = shutter control register value href ofdx ofdw notes: ofdx remains high when shutter is set to 00h. line #s shown are for 525 line system. figure 13. electronic shutter control signal timing
cs7615 14 ds231pp6 symbol description register hbpd horizontal blanking period 40h hlen total number of horizontal pixels 41h, 42h hsynr href to hsync leading edge 43h hsynf href to hsync trailing edge 44h bc href to clamp leading edge (clamp trailing edge at hend) 45h hend href to henb leading edge 46h hstart hz. clock disable period 47h v1r v1 clock leading edge 48h v1f v1 clock trailing edge 47h v2r v2 clock leading edge 4ah v2f v2 clock trailing edge 4bh v3f v3 clock leading edge 4ch v3r v3 clock trailing edge 4dh v4f v4 clock leading edge 4eh v4r v4 clock trailing edge 4fh v2or v2odd clock leading edge 50h, 52h v2of v2odd clock trailing edge 51h, 52h v3of v3odd clock leading edge 53h, 55h v3or v3odd clock trailing edge 54h v2er v2even clock leading edge 56h, 58h v2ef v2even clock trailing edge 57h v3ef v3even clock leading edge 59h, 5bh v3er v3even clock trailing edge 5ah v4ef v4even clock leading edge 5ch, 5eh v4er v4even clock trailing edge 5dh vh1f charge read clock leading edge 5fh, 61h vh1r charge read clock trailing edge 60h, 61h vh3f charge rd clock leading edge 62h, 64h vh3r charge rd clock trailing edge 63h, 64h ofdw ofdw pulse width 65h table 2. horizontal timing specifications
cs7615 ds231pp6 15 analog to digital converter after the pixel data is double sampled and the ap- propriate gain has been applied, it is digitized by the internal 10-bit a/d converter. these resulting mosaic data are input to the formatter which for- mats the data before sending it to the chip output. the output of the a/d converter is also used by the internal agc loop in determining the proper gain setting, and by the black level adjust when reading the black pixels. black level adjust to code 16 (10-bit code 64) the output data are adjusted to hold the image black level at the 8-bit code of 16, in compliance to the itu-601 recommendation. during the blanking periods, the black level adjustment is updated when over black pixels. the number of black pixels used is programmable by the user through the i 2 c inter- face. formatter the formatter adds the necessary eav/sav timing codes to the output data in accordance with the itu-656 recommendation.
cs7615 16 ds231pp6 serial control bus the serial control bus protocol is an 8-bit protocol controlled receiver. to the receiver, the control bus looks like an 8-bit bi-directional channel down which short packets are sent or received. each source device appears to the receiver as a set of 8- bit registers, which are addressable to a device through a station address. packets are used to write and read the contents of these device registers. there are three packet formats: write format, address set format, and read format. each packet is addressed to a device by its station ad- dress. the lsb of the station address is the data di- rection bit. this bit is set low in the write and address set packets, and it is set high for read packets. the receiver can read and write to non-existent registers within the selected device. write operations will have no effect; read op- erations will return a value of 00h. station address the cs7615 rev a default station address is a8h for writes and a9h for reads. subsequent versions of the cs7615, starting with rev b, will use a de- fault station address of 68h for writes and 69h for reads. the station address can be changed by writing a new base station address to internal i 2 c register feh. note that the station address register de- scribes only the 7 msbs of the cs7615 station ad- dress. the base write address will need to be right shifted by one place before being written into the feh register. write operations the write format consists of a three-byte packet. the first byte is the station address with the data di- rection bit set low to indicate a write. the second byte is the device register address (0..255). the third byte is the register data (0..255). no extra bytes should be sent. table 3. write format packet address set operation the address set format consists of a two-byte packet which sets the address of a subsequent read operation. the first byte of the station ad- dress with the lsb (data direction bit) set low to indicate a write operation. the second byte is the register address (0..255). the address set for- mat is the same as the write format, without the register data. table 4. address set format packet operation read operations the read operation consist of two or more bytes. the first byte is the station address with the lsb (data direction bit) set high indicating a read op- eration. the addressed device then sends one or more bytes back from the register last addressed by the previous write operation, or address set operation. table 5. read format packet. byte sequence write format packet detail first byte station address with lsb set low second byte device register address (0..255) third byte register data (0..255) byte sequence address set format packet details first byte station address with lsb set low second byte device register address (0..255) byte sequence read format packet details first byte station address with lsb set high; source device then returns one byte of register data (0..255) second byte returned data from cs7615
cs7615 ds231pp6 17 register descriptions software reset register (00h) sr4 setting bit sr4 to logic high will initiate a cs7615 software reset. software reset resets all the digital blocks except for i 2 c and the adc calibration logic. the clocks remain running. this reset bit automatically clears. low power register (20h) pd4 setting bit pd4 to logic high will place the cs7615 chip in a low power mode. the i 2 c interface and clock generation circuitry will remain powered up. operational control #1 register (24h) pal logic high indicates a pal standard camera system, logic low indicates ntsc. default = 0. agcw used to window the portion of the frame to use for agc. default = 00. 00 = use entire frame 01 = use center 1/4 area of frame 10 = use center 1/16 area of frame 11 = reserved agcdi logic high disables cs7615s automatic gain control circuitry. user may manually control gain through the gain register 25h/26h. default = 0. agcalg controls data used in cs7615s agc loop. logic high indicates mosaic data, logic low indicates luma data. default = 0. ccdtyp logic high signifies that a type b ccd is being used, logic low signifies a type a ccd. default = 0. flckls logic high restricts shutter to flickerless settings. default = 0. palenv logic high when the camera system is being used in a pal environment, logic low in an ntsc environment. default = 0. r/w read/write r read wwrite res reserved 76543210 res res res sr4 res res res res rrrwrrrr 76543210 res res res pd4 res res res res rrrr/wrrrr 76543210 pal agcw1 agcw2 agcdis agccalg ccdtyp flckls palenv r/w r/w r/w r/w r/w r/w r/w r/w
cs7615 18 ds231pp6 gain registers (25-26h) 25h: 26h: agc(10:0) gain control word for the automatic gain control. this 11 bit word is a 2s compliment number which has a minimum value of -784 (decimal) (reg 26h = 04h; reg 25h = 5f0h) for pal or - 765d for ntsc (reg 26h = 05h; reg 25h = 03) and a maximum value of 484d (reg 26h = 01h; reg 25h = e4h). the gain range is -54 db to 38 db in steps of 0.078 db ideal, 0.12 db max step is guaranteed only for chip gain. default is 000h. agc error statistic register (27h): agcer the 8 msbs of the gain error statistic calculated as part of the agc loop. agc count statistic register (28h) agcct the output of the 1-of-7 block which denotes the bin where the agc target was met. agc target value register (29h) agctg the target value used in the agc loop. it denotes the number of pixels that must be exceeded for an intensity bin to give an output of 1. default is 0h. 000=64 100=1024 001=128 101=2048 010=256 110=4096 011=512 111=8192 76543210 agc10 agc9 agc8 agc7 agc6 agc5 agc4 agc3 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res agc2 agc1 agc0 rrrrrr/wr/wr/w 76543210 agcer7 agcer6 agcer5 agcer4 agcer3 agcer2 agcer1 agcer0 rrrrrrrr 76543210 res agcct6 agcct5 agcct4 agcct3 agcct2 agct1 agcct0 rrrrrrrr 76543210 res res res res res agctg2 agctg1 agctg0 rrrrrr/wr/wr/w
cs7615 ds231pp6 19 agc maximum gain register (2ah) mgn sets the maximum gain allowable if the user chooses to limit the chip gain beyond a certain value. the range is 0-242, with the actual max gain word being twice this value. default is f2h. agc slew and speed register (2bh) slew sets the rate of decay of gain when the gain target is exceeded in the maximum intensity bin. default is 0h. 00 = -8 10 = -32 01 = -16 11 = -64 spd varies the agc loop gain. the error signal used for correction is multiplied by the speed num- ber before being added to the accumulator. default is 0h. 00 = 1x 10 = 4x 01 = 2x 11 = 8x agc minimum gain register (2ch) mngn sets the minimum gain allowable if the user chooses to limit the chip gain from a certain value. default is 00h. ccd signal alignment register (2dh) these signals adjust the edges of h1 or fr with respect to the internal sampling clock. hr adjusts the location of the rising edge of h1. hf adjusts the location of the falling edge of h1. frr adjusts the location of the rising edge of fr. frf adjusts the location of the falling edge of fr. 76543210 mgn7 mgn6 mgn5 mgn4 mgn3 mgn2 mgn1 mgn0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res slew1 slew0 spd1 spd0 rrrrr/wr/wr/wr/w 76543210 mng7 mng6 mng5 mng4 mng3 mng2 mng1 mng0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 hr1 hr0 hf1 hf0 frr1 frr0 frf1 frf0 r/w r/w r/w r/w r/w r/w r/w r/w
cs7615 20 ds231pp6 vrst registers (2eh, 2fh) 2eh: 2fh: these parameters are needed only when the vrst input is used. vrstn the line number gets reset to this value on a negative edge of vrst. default is 004h. vrstdy logic high denotes vrst will be delayed with respect to the line position. default = 0 (no delay). vrstfld logic high denotes the field is reset to even on a negative edge of vrst, logic low denotes the field is reset to odd. default = 0. maximum shutter exposure register (30h) mxsh if the user chooses to limit the exposure time, the max shutter gain is set to this value. 00h=full exposure, bfh=min exposure for ntsc, c4h= min exposure for pal. operational control #2 register (31h) blkdis logic high disables the black level loop. black level remains at the current value. default =0. adcal1 analog-to-digital converter option. when written to a logic high, calibration is immediately en- tered. this bit goes back low when calibration is complete. adcal2 analog-to-digital converter option. logic high results in calibration being done after every frame, logic low results in calibration only on power up. default = 0. cnvfst logic high sets the frequency of hclk to 16the line frequency, logic low sets hclk to 1the line frequency. default = 0. 76543210 vrstn8 vrstn7 vrstn6 vrstn5 vrstn4 vrstn3 vrstn2 vrstn1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res vrstdy vrstfld vrstn0 rrrrrr/wr/wr/w 76543210 msxh7 msxh6 msxh5 msxh4 msxh3 msxh2 msxh1 msxh0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res blkdis adcal1 adcal2 cnvfst rrrrr/wr/wr/wr/w
cs7615 ds231pp6 21 timing control- line number registers (33h-39h) 33h: 34h: 35h: 36h: 37h: 38h: 39h: vlo the number of lines in an odd field. default is 106h. vle the number of lines in an even field. default is 107h. vbe line number for end of vref for even field. default is 013h. vbo line number for end of vref for odd field. default is 012h. xse line number for charge transfer for even field. default is 011h. xso line number for charge transfer for odd field. default is 010h. 76543210 vlo8 vlo7 vlo6 vlo5 vlo4 vlo3 vlo2 vlo1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 vle8 vle7 vle6 vle5 vle4 vle3 vle2 vle1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 vbe8 vbe7 vbe6 vbe5 vbe4 vbe3 vbe2 vbe1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 vbo8 vbo7 vbo6 vbo5 vbo4 vbo3 vbo2 vbo1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 xse8 xse7 xse6 xse5 xse4 xse3 xse2 xse1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 xso8 xso7 xso6 xso5 xso4 xso3 xso2 xso1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res vlo0 vle0 vbe0 vbo0 xse0 xso0 r r r/w r/w r/w r/w r/w r/w
cs7615 22 ds231pp6 timing control-horizontal blank pd register (40h) hbpd number of pixel clocks in the horizontal blank period. default is 70h. timing control- line length register (41h-42h) 41h: 42h: hlen total number of pixels in line length. default is 270h. timing control- hsync registers (43h-44h) 43h: 44h: hsynr number of pixels from href to leading edge of hsync. default is 14h. hsynf number of pixels from href to trailing edge of hsync. default is 44h. timing control - black clamp register (45h) bc number of pixels from href to leading edge of black clamp. default is 08h. black clamp falls on leading edge of henb. 76543210 hbpd7 hbpd6 hbpd5 hbpd4 hbpd3 hbpd2 hbpd1 hbpd0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 hlen9 hlen8 hlen7 hlen6 hlen5 hlen4 hlen3 hlen2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res hlen1 hlen0 rrrrrrr/wr/w 76543210 hsynr7 hsynr6 hsynr5 hsynr4 hsynr3 hsynr2 hsynr1 hsynr0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 hsynf7 hsynf6 hsynf5 hsynf4 hsynf3 hsynf2 hsynf1 hsynf0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 r/w r/w r/w r/w r/w r/w r/w r/w
cs7615 ds231pp6 23 timing control - henb registers (46h-47h) 46h: 47h: hend number of pixels from href to leading edge of henb. default is 1ch. hstart number of pixels from href to trailing edge of henb. default is 68h. timing control - v1x registers (48h-49h) 48h: 49h: v1x is a vertical register shift clock. v1r number of pixels from href to leading edge of v1x. default is 22h. v1f number of pixels from href to trailing edge of v1x. default is 36h. 76543210 hend7 hend6 hend5 hend4 hend3 hend2 hend1 hend0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 hstart7 hstart6 hstart5 hstart4 hstart3 hstart2 hstart1 hstart0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v1r7 v1r6 v1r5 v1r4 v1r3 v1r2 v1r1 v1r0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v1f7 v1f6 v1f5 v1f4 v1f3 v1f2 v1f1 v1f0 r/w r/w r/w r/w r/w r/w r/w r/w
cs7615 24 ds231pp6 timing control - v2x registers (4ah-4bh) 4ah: 4bh: v2x is a vertical register shift clock. v2r number of pixels from href to leading edge of v2x. default is 2ch. v2f number of pixels from href to trailing edge of v2x. default is 40h. timing control - v3x registers (4ch-4dh) 4ch: 4dh: v3x is a vertical register shift clock. v3f number of pixels from href to leading edge of v3x. default is 1dh. v3r number of pixels from href to trailing edge of v3x. default is 3bh. 76543210 v2r7 v2r6 v2r5 v2r4 v2r3 v2r2 v2r1 v2r0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v2f7 v2f6 v2f5 v2f4 v2f3 v2f2 v2f1 v2f0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v3f7 v3f6 v3f5 v3f4 v3f3 v3f2 v3f1 v3f0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v3r7 v3r6 v3r5 v3r4 v3r3 v3r2 v3r1 v3r0 r/w r/w r/w r/w r/w r/w r/w r/w
cs7615 ds231pp6 25 timing control - v4x registers (4eh-4fh): 4eh: 4fh: v4x is a vertical register shift clock. v4f number of pixels from href to leading edge of v4x. default is 29h. v4r number of pixels from href to trailing edge of v4x. default is 45h. timing control - charge read out in odd field v2x registers (50h-52h) 50h: 51h: 52h: charge readout timing for v2x in an odd field in number of pixels. v2or from href to leading edge of v2x. default is 185h. v2of from href to trailing edge of v2x. default is 1e9h. 76543210 v4f7 v4f6 v4f5 v4f4 v4f3 v4f2 v4f1 v4f0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v4r7 v4r6 v4r5 v4r4 v4r3 v4r2 v4r1 v4r0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v2or9 v2or8 v2or7 v2or6 v2or5 v2or4 v2or3 v2or2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v2of9 v2of8 v2of7 v2of6 v2of5 v2of4 v2of3 v2of2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res v2of1 v2of0 v2or1 v2or0 rrrrr/wr/wr/wr/w
cs7615 26 ds231pp6 timing control - charge read out in odd field v3x registers (53h-55h) 53h: 54h: 55h: charge readout timing for v3x in an odd field in number of pixels. v3of from href to leading edge of v3x. default is 188h. v3or from href to trailing edge of v3x. default is 3bh. timing control - charge read out in even field v2x registers (56h-58h) 56h: 57h: 58h: charge readout timing for v2x in an even field in number of pixels. v2er from href to leading edge of v2x. default is 185h. v2ef from href to trailing edge of v2x. default is 40h. 76543210 v3of9 v3of8 v3of7 v3of6 v3of5 v3of4 v3of3 v3of2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v3or7 v3or6 v3or5 v3or4 v3or3 v3or2 v3or1 v3or0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res v3of1 v3of0 rrrrrrr/wr/w 76543210 v2er9 v2er8 v2er7 v2er6 v2er5 v2er4 v2er3 v2er2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v2ef7 v2ef6 v2ef5 v2ef4 v2ef3 v2ef2 v2ef1 v2ef0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res v2er1 v2er0 rrrrrrr/wr/w
cs7615 ds231pp6 27 timing control - charge read out in even field v3x registers (59h-5bh) 59h: 5ah: 5bh: charge readout timing for v3x in an even field in number of pixels. v3ef from href to leading edge of v3x. default is 188h. v3er from href to trailing edge of v3x. default is 3bh. timing control - charge read out in even field v4x registers (5ch-5eh) 5ch: 5dh: 5eh: charge readout timing for v4x in an even field in number of pixels. v4ef from href to leading edge of v4x. default is 1e9h. v4er from href to trailing edge of v4x. default is 45h. 76543210 v3ef9 v3ef8 v3ef7 v3ef6 v3ef5 v3ef4 v3ef3 v3ef2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v3er7 v3er6 v3er5 v3er4 v3er3 v3er2 v3er1 v3er0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res v3ef1 v3ef0 rrrrrrr/wr/w 76543210 v4ef9 v4ef8 v4ef7 v4ef6 v4ef5 v4ef4 v4ef3 v4ef2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 v4er7 v4er6 v4er5 v4er4 v4er3 v4er2 v4er1 v4er0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res v4ef1 v4ef0 rrrrrrr/wr/w
cs7615 28 ds231pp6 timing control - h1x registers (5fh-61h) 5fh: 60h: 61h: charge read out timing for vh1x in number of pixels. vh1f from href to leading edge of vh1x. default is 18fh. vh1r from href to trailing edge of vh1x. default is 1adh. timing control - vh1x registers (62h-64h) 62h: 63h: 64h: charge read out timing for vh3x in number of pixels. vh3f from href to leading edge of vh3x. default is 1b7h. vh3r from href to trailing edge of vh3x. default is 1d5h. 76543210 vh1f9 vh1f8 vh1f7 vh1f6 vh1f5 vh1f4 vh1f3 vh1f2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 vh1r9 vh1r8 vh1r7 vh1r6 vh1r5 vh1r4 vh1r3 vh1r2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res vh1r1 vh1r0 vh1f1 vh1f0 rrrrr/wr/wr/wr/w 76543210 vh3f9 vh3f8 vh3f7 vh3f6 vh3f5 vh3f4 vh3f3 vh3f2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 vh3r9 vh3r8 vh3r7 vh3r6 vh3r5 vh3r4 vh3r3 vh3r2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res vh3r1 vh3r0 vh3f1 vh3f0 rrrrr/wr/wr/wr/w
cs7615 ds231pp6 29 black level adjust register (68h) blk offset added to input of adc so that the output of adc during black pixels is code 64. 00h-ffh represents a voltage range of 0-186mv. default is 8fh. this register is automatically updated when black level adjust is enabled. version (minor) register (69h) the minor version register in the cs7615 rev a is assigned the value 00h. the rev b device is assigned the value 01h. with each minor version the value is increased by 1. version (major) register (6ah) the major version register in the cs7615 rev a is assigned the value ffh. with each major version the value is decreased by 1. station address register (feh) sta cs7615s station address, 7 msbs (lsb of complete 8-bit station address determined by read/write bit). 76543210 blk7 blk6 blk5 blk4 blk3 blk2 blk1 blk0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 76543210 rrrrrrrr 76543210 76543210 rrrrrrrr 76543210 res sta6sta5sta4sta3sta2sta1sta0 r r/w r/w r/w r/w r/w r/w r/w
cs7615 30 ds231pp6 pin descriptions power supply connections vaa - analog power supply, pin 19, 21. nominally +5 volts. vdd - digital power supply, pin 5, 41. nominally +5 volts. 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 CS7615-KQ 44-pin tqfp top view gndd vdd vh1x clko do9(msb) do8 do7 do6 do5 do4 vdd gndd clk2xo gnda gnda reset fclkin gnda interp vrst scl sda hsync v1x v2x ofdx xtalin xtalout hclk do0(lsb) do1 do2 do3 ain gnda vaa fr vaa gnda h1 h2 v4x vh3x v3x
cs7615 ds231pp6 31 gnda - analog ground, pin 12, 15, 16, 18, 22. analog ground reference. gndd - digital ground, pin 6, 40. digital ground reference. analog input ain - video input, pin 17. ccd output signal. digital inputs vrst - vertical sync reset, pin 10. used to reset vertical line counter in genlock mode. vrst is falling edge triggered. interp - digital video horizontal data rate scaler enable, pin 11. active high logic input sets clko output rate to 1 non-interpolated data rate, and the clk2xo output rate to 2 interpolated data rate (5/2 clko rate). logic low causes the clko output rate to be the pixel rate, while clkx2o is set to twice the pixel rate. fclkin - frequency of crystal input, pin 13. logic input identifying the external crystal as a 1 rate or a 2 rate crystal. this pin should be set high for a 1 crystal or clock source; logic low for a 2 crystal or clock source. reset - master reset, pin 14. may be connected to external power-on-reset-circuit. clears registers to default values. active logic high. xtalin - crystal input, pin 32. may be 1 or 2 the data rate. xtalout - oscillator output to crystal, pin 33. if the on-chip oscillator is used, this output connects to the crystal. timing generator outputs hsync - horizontal sync signal, pin 7. to be used in genlock mode. hsync is a rising pulse.
cs7615 32 ds231pp6 fr- reset gate clock pulse for ccd, pin 20. connect directly to ccd. fr is a rising pulse. h1- horizontal shift register clock #1, pin 23. connect directly to ccd. h2- horizontal shift register clock #2, pin 24. connect directly to ccd. v4x- vertical shift register clock, pin 25. connects to vertical driver. vh3x- charge read out pulse, pin 26. connect to vertical driver. v3x- vertical shift register clock, pin 27. connects to vertical driver. vh1x- charge read out pulse, pin 28. connect to vertical driver. v1x- vertical shift register clock, pin 29. connects to vertical driver. v2x- vertical shift register clock, pin 30. connects to vertical driver. ofdx- charge sweep out pulse for shutter control, pin 31. connect to vertical driver. ofdx is a falling pulse. hclk- horizontal line frequency clock, pin 34. connect to dc-dc converter. hclk is a falling pulse when it is in href output mode. mosaic data and clock outputs d o[0..9] - digital mosaic outputs. cmos level mosaic coded ccd output data.
cs7615 ds231pp6 33 clko - mosaic output data clock, pin 4. main system output clock, used to strobe outgoing digital ccd mosaic data. data transitions on the falling edge. clk2xo - mosaic output data interpolation clock, pin 39. mosaic output data interpolation clock. 2x the clko frequency in normal mode (non- interpolated output data... see interp description), and 2.5 the clko frequency when a 4:5 horizontal data rate scaler is used in the color processor. i 2 c serial control sda - primary i 2 c data bus, pin 8. primary i 2 c data bus. used with scl to read and write the internal register set. scl - primary i 2 c clock, pin 9. primary i 2 c clock. used with sda to read and write the internal register set. pin name pin function pin number d o0(lsb) digital mosaic output (lsb) 35 d o1 digital mosaic output 36 d o2 digital mosaic output 37 d o3 digital mosaic output 38 d o4 digital mosaic output 42 d o5 digital mosaic output 43 d o6 digital mosaic output 44 d o7 digital mosaic output 1 d o8 digital mosaic output 2 d o9(msb) digital mosaic output (msb) 3 table 6. digital mosaic outputs.
cs7615 34 ds231pp6 package dimensions inches millimeters dim min max min max a 0.000 0.065 0.00 1.60 a1 0.002 0.006 0.05 0.15 b 0.012 0.018 0.30 0.45 d 0.478 0.502 11.70 12.30 d1 0.404 0.412 9.90 10.10 e 0.478 0.502 11.70 12.30 e1 0.404 0.412 9.90 10.10 e 0.029 0.037 0.70 0.90 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 jedec # : ms-026 44l tqfp package drawing e1 e d1 d 1 e l b a1 a
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